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preliminary this is a product in the pre - production phase of development. device characterization is complete and ramtron does not expect to change the specifications. ramtron will issue a product change notice if any specification changes are m ade. cypress semiconductor corporation ? 198 champion court ? san jose, ca 95134 - 1709 ? 408 - 943 - 2600 document number: 001 - 86601 rev. ** revised march 12 , 2013 fm 28v 102 1m bit (64k 16) f - ram memory features 1 m bit ferroelectric nonvolatile ram organized as 64k x16 configurable as 128 kx8 using /ub, /lb 10 14 read/write cycles nodelay? writes page mode operation to 33 mhz advanced high - reliability ferroelectric proce ss sram compatible industry std. 64k x16 sram p inout 60 ns access time, 90 ns cycle time superior to battery - backed sram modules no b attery c oncerns monolithic r eliability true s urface m ount s olution, n o r ework s teps superior for m oisture, s hock, and v ibration low power operation 2.0v C 3.6v power supply standby current 12 0 a (typ) active current 7 ma (typ) industry standard configuration industrial temperature - 40 c to +85 c 44 - pin green/rohs tsop - ii package description the fm 28v 102 is a 64k x16 nonvolatile memory that reads and writes like a standard sram. a ferroe lectric random access memory or f - ram is nonvolatile, which means that data is retained after power is removed. it provides data retention for over 10 years while eliminating the reliability concerns, functional disadvantages, and system design complexitie s of battery - backed sram (bbsram). fast write timing and high write endurance make the f - ram superior to other types of memory. in - system operation of the fm 28v 102 is very similar to other ram devices and can be used as a drop - in replacement for standard sram. read and write cycles may be triggered by /ce or simply by changing the address. the f - ram memory is nonvolatile due to its unique ferroelectric memory process. these features make the fm 28v 102 ideal for nonvolatile memory applications requiring fre quent or rapid writes in the form of an sram . the device is available in a 400 mil 44 - pin t sop - ii surface mount package . device specifications are guaranteed over industrial tem perature range C 40c to +85c. pin configuration 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 n c / z z o e a 7 a 6 a 5 v s s d q 1 2 d q 1 1 d q 8 d q 9 d q 1 0 l b a 8 a 9 a 1 0 a 1 1 v d d u b d q 1 3 d q 1 4 d q 1 5 a 4 a 3 a 2 a 1 a 0 a 1 2 a 1 3 d q 0 d q 1 d q 2 v s s d q 3 d q 4 d q 5 d q 6 d q 7 w e v d d a 1 4 a 1 5 v s s c e
FM28V102 - 64kx16 f - ram document number: 001 - 86601 rev. ** page 2 of 1 6 figure 1. block diagram pin description pin name type pin description a( 15: 0) input addre ss inputs: the 16 add ress lines select one of 64k words in the f - ram array. the lowest two address lines a(1:0) may be used fo r page mode read and write operations. /ce input chip enable input s : the device is selected and a new memory access begins on the falling edge of /ce. the entire address is latched internally at this point. subsequent changes to the a(1:0) address inputs allow page mode operation. /we input write enable: a write cycle begins when /we is asserted. the rising edge causes the fm 28v 102 to write the data on the dq bus to the f - ram array. the falling edge of /we latche s a new column address for page mode writ e cycles . /oe input output enable: when /oe is low, the fm 28v 102 drives the data bus when valid read data is available. deasserting /oe high tri - states the dq pins. /zz input sleep: when /zz is low, the device enters a low power sleep mode for the lowes t supply current condition. since this input is logically andd with /ce, /zz must be high for normal read/write operation. the / zz pin is internally pulled up . dq(15:0) i/o data: 16 - bit bi - directional data bus for accessing the f - ram array. /ub input u pper byte select: enables dq(15:8) pins during reads and writes. these pins are hi - z if /ub is high. if the user does not perform byte writes and the d evice is not configured as a 128 kx8, the /ub and /lb pins may be tied to ground. /lb input lower byte se lect: enables dq(7:0) pins during reads and w rites. these pins are hi - z if / l b is high. if the user does not perform byte writes and the d evice is not configured as a 128 kx8, the /ub and /lb pins may be tied to ground. vdd supply supply voltage vss supp ly ground a d d r e s s l a t c h & w r i t e p r o t e c t c e 1 , c e 2 c o n t r o l l o g i c w e b l o c k & r o w d e c o d e r a ( 1 5 : 2 ) a ( 1 : 0 ) i / o l a t c h & b u s d r i v e r o e d q ( 1 5 : 0 ) 1 6 k x 6 4 f - r a m a r r a y a ( 1 5 : 0 ) . . . c o l u m n d e c o d e r . . . u b , l b 2 z z
FM28V102 - 64kx16 f - ram document number: 001 - 86601 rev. ** page 3 of 1 6 table 1. functional truth table 1,2 /ce /we a( 15: 2) a(1:0) /zz operation x x x x l sleep mode h x x x x x x x h standby/idle l h h v v v v h read l h no change change h page mode read l h change v h random read l l l v v v v h /ce - controlled write 2 l v v h /we - controlled write 2, 3 l no change v h page mode write 4 l x x x x x x h starts precharge notes: 1) h=log ic high, l=logic low, v=valid data, x=dont care. 2) for write cycles, data - in is latched on the rising edge of / ce o r /we , whichever comes first. 3) /we - controlled write cycle begins as a read cycle and a( 15: 2 ) is latched then . 4) a ddresses a(1 :0) must remain stab le for at least 15 ns during page mode operation . table 2. byte select truth table /we /oe /lb /ub operation h h x x read; outputs disabled x h h h l h l read upper byte; hi - z lower byte l h read lower byte; hi - z upper byte l l read both byt es l x h l write upper byte; mask lower byte l h write lower byte; mask upper byte l l write both bytes the /ub and /lb pins may be grounded if 1) the system does not perform byte writes and 2) the d evice is not configured as a 128 kx8. simplifie d sleep/standby state diagram i n i t i a l i z e n o r m a l o p e r a t i o n s t a n d b y s l e e p p o w e r a p p l i e d / z z l o w / z z h i g h / c e h i g h , / z z h i g h / c e l o w , / z z h i g h / c e l o w , / z z h i g h / z z l o w / c e h i g h , / z z h i g h
FM28V102 - 64kx16 f - ram document number: 001 - 86601 rev. ** page 4 of 1 6 overview the fm 28v 102 is a wordwide f - ram memory logically organized as 65,536 x 16 and accessed using an industry standard parallel interface. all data written to the part is immediately nonvo latile with no delay. the device offers page mode operation which provides higher speed access to addresses within a page (row). an access to a different page requires that either /ce transitio ns low or the upper address a( 15: 2) changes. memory operation users access 65,536 memory locations, each with 16 data bits through a parallel interface. the f - ram array is organi zed as 16,384 rows each having 64 bits . each row has 4 column locations, which allows fast access in page mode operation. once an initial ad dress has been latched by the falling edge of /ce, subsequent column locations may be accessed without the need to toggle /ce. when /ce is deasserted high, a precharge operation begins. writes occur immediately at the end of the access with no delay. the /we pin must be toggled for each write operation . the write data is stored in the nonvolatile memory array immediately, which is a feature unique to f - ram called nodelay tm writes. read operation a read operation begins on the falling edge of /ce. the fal ling edge of /ce causes the address to be latched and starts a memory read cycle if /we is high. data becomes available on the bus after the access time has been satisfied. once the address has been latched and the access completed, a new access to a rand om location (different row) may begin while /ce is still low. the minimum cycle time for random addresses is t rc . note that unlike srams, the fm 28v 102 s /ce - initiated access time is faster than the address cycle time. the fm 28v 102 will drive the data bus when /oe and at least one of the byte enables (/ub, /lb) is asserted low. the upper data byte is driven when /ub is low, and the lower data byte is driven when /lb is low. if /oe is asserted after the memory access time has been satisfied, the data bus wi ll be driven with valid data. if /oe is asserted prior to completion of the memory access, the data bus will not be driven until valid data is available. this feature minimizes supply current in the system by eliminating transients caused by invalid data b eing driven onto the bus. when /oe is deasserted high, the data bus will remain in a high - z state. write operation writes occur in the fm 28v 102 in the same time interval as reads. the fm 28v 102 supports both /ce - and /we - controlled write cycles. in both c ases, the address a( 15: 2) is latched on the falling edge of /ce . in a /ce - controlled write, the /we signal is asserted prior to beginning the memory cycle. that is, /we is low when /ce falls. in this case, the device begins the memory cycle as a write. th e fm 28v 102 will not drive the data bus regardless of the state of /oe as long as /we is low. input data must be valid when /ce is deasserted high. in a /we - controlled write, the memory cycle begins on the falling edge of /ce. the /we signal falls some tim e later. therefore, the memory cycle begins as a read. the data bus will be driven if /oe is low, however it will hi - z once /we is asserted low. the /ce - and /we - controlled write timing cases are shown in the electrical specifications section. write acce ss to the array begins on the falling edge of /we after the memory cycle is initiated. the write access terminates on the rising edge of /we or /ce, whichever comes first. a valid write operation requires the user to meet the access time specification prio r to deasserting /we or /ce. data setup time indicates the interval during which data cannot change prior to the end of the write access ( rising edge of /we or /ce ). unlike other truly nonvolatile memory technologies, there is no write delay with f - ram . since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. the entire memory operation occurs in a single bus cycle. data polling, a technique used with eeproms to determine if a write is com plete, is unnecessary. page mode operation the f - ram array is organi zed as 16,384 rows each having 64 bits . each row has 4 column address locations. address inputs a(1:0) define the column address to be accessed. an access can start on any column address, and other column locations may be accessed without the need to toggle the /ce pin. for fast access reads, once the first data byte is driven onto the bus, the column address inputs a(1:0) may be changed to a new value. a new data byte is then driven to the dq pins no later than t aa p , which is less than half the initial read access time. for fast access writes, the first write pulse defines the first write access. while /ce is low, a subsequent write pulse along with a new column address provides a page mode write access .
FM28V102 - 64kx16 f - ram document number: 001 - 86601 rev. ** page 5 of 1 6 precharge operation the precharge operation is an internal condition in which the state of the memory is being prepared for a new access. precharge is user - initiated by driving the /ce signal high. it must remain high for at least the m inimum precharge time t pc . precharge is also activated by changing the upper addess a( 15: 2). the current row is first closed prior to accessing the new row. the device automatically detects an upper order address change which starts a precharge operati on, the new address is latched, and the new read data is valid within the t aa address access time. refer to the read cycle timing 1 diagram. likewise a similar sequence occurs for write cycles. refer to the write cycle timing 3 diagram . the rate at which random addresses can be issued is t rc and t wc , respectively. sleep mode the device incorporates a sleep mode of operation which allows the user to achieve the lowest power supply current condition. it enters a low power sleep mode by asserting the /zz pin low . read and write operations must complete prior to the /zz pin going low. once /zz is low, all pins are ignored except the /zz pin. when /zz is deasserted high, there is some time delay (t zzex ) before the user can access the device. if sleep mode i s not used, the /zz pin may be floated (internal pullup) or tied to v dd . sram drop - in replacement the fm 28v 102 has been designed to be a drop - in replacement for standard asynchronous srams. the device does not require /ce to toggle for each new address. /ce may remain low indefinitely. while /ce is low, the device automatically detects address chan ges and a new access is begun. this functionality allows /ce to be grounded as you might with an sram. it also allows page mode operation at speeds up to 33 mhz. note that if /ce is tied to ground, the user must be sure /we is not low at powerup or powerdown events. if /ce and /we are both low during power cycles, data corruption will occur. figure 5 shows a pullup resistor on /we which will keep the pin high during power cycles assuming the mcu/mpu pin tri - states during the reset condition. the pullup resistor value should be chosen to ensure the /we pin tracks v dd yet a high enough value that the current drawn when /we is low is not an issue. a 10kohm resistor draws 330ua when /we is low and v dd =3.3v. note that software write - protect is not available to the user if the chip enable pins are hardwired active. figure 2 . use of pullup resistor on /we for applications that req uire the lowest power consumption, the /ce signal should be active (low) only during memory accesses. the fm 28v 102 draws supp ly current while /ce is low, even if addresses and control signals are static. while /ce is high, the device draws no more than th e maximum standby current i sb . the fm 28v 102 i s compatible with the 2 mbit fm2 8v202 device . there are some differences in the timing specificatio ns. pl ease refer to the fm28v202 datasheet . the /ub and /lb byte select pins are active for both read and writ e cycles. they may be used to allow the device to be wired as a 128 kx8 memory. the upper and lower data bytes can be tied together and controlled with the byte selects. individual byte enables or the next higher address line a(16 ) may be available from t he system processor. ce we oe a(15:0) dq fm28v 102 v dd mcu/ mpu r
FM28V102 - 64kx16 f - ram document number: 001 - 86601 rev. ** page 6 of 1 6 figure 3 . fm 28v 102 wired as 128 kx8 pcb layout recommendations a 0.1uf decoupling capacitor should be placed close to pin 11 (v dd ) and the ground side of the capacitor should be connected to either a groun d plane or low impedance path back to pin 12 (v ss ). the same should be done to the other side at pins 33 and 34. this is especially important for the tsop - ii package due to the inductance of the leadframe . it is best to use a chip capacitor that has a low esr and has good high frequency characteristics. if the controller drives the address and chip enable from the same timing edge, it is best to keep the address routes short and of equal length. a simple rc circuit may be inserted in the chip enable path to provide some delay and timing margin for the fm28v 102 s address setup time t as . as a general rule, the layout designer may need to add series termination resistors to controller outputs that have fast transitions or routes that are > 15cm in length. t his is only necessary if the edge rate is less than or equal to the round trip trace delay. signal overshoot and ringback may be large enough to cause erratic device behavior. it is best to add a 50 ohm resistor (30 C 60 ohms) near the output driver (cont roller) to reduce such transmission line effects. d q ( 1 5 : 8 ) d q ( 7 : 0 ) d ( 7 : 0 ) a ( 1 5 : 0 ) / c e / u b / l b / w e / o e / z z 1 m b i t f r a m f m 2 8 v 1 0 2 a ( 1 6 ) a ( 1 5 : 0 )
FM28V102 - 64kx16 f - ram document number: 001 - 86601 rev. ** page 7 of 1 6 endurance the fm28v 102 is capable of being accessed at least 10 14 times C reads or writes. an f - ram memory operates with a read and restore mechanism. therefore, an endurance cycle is applied on a r ow basis. the f - ram architecture is based on an array of rows and columns. rows are defined by a15 - a2 and column addresses by a1 - a0. the array is organized as 16 k rows of 4 - words each. the entire row is internally accessed once whether a single 16 - bit word or all four words are read or written. each word in the row is counted only once in an endurance calculation. the user may choose to write cpu instructions and run them from a certain address space. the table below shows endurance calculations for 256 - b yte repeating loop, which includes a starting address, 3 page mode accesses, and a ce precharge. the number of bus clocks needed to complete a 4 - word transaction is 4+1 at lower bus speeds, but 5+2 at 33mhz due to initial read latency and an extra clock to satisfy the devices precharge timing constraint t pc . the entire loop causes each byte to experience only one endurance cycle. f - ram read and write endurance is virtually unlimited even at 33mhz system bus clock rate. table 3. time to reach 100 trill ion cycles for repeating 256 - byte loop bus freq (mhz) bus cycle time (ns) 256 - byte transaction time ( s) endurance cycles/sec. endurance cycles/year years to reach 10 14 cycles 33 30 10.56 94,690 2.98 x 10 12 33.5 25 40 12.8 78,125 2.46 x 10 12 40.6 10 100 28.8 34,720 1.09 x 10 1 2 91.7 5 200 57.6 17,360 5.47 x 10 1 1 182.8
FM28V102 - 64kx16 f - ram document number: 001 - 86601 rev. ** page 8 of 1 6 electrical specifica tions absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss - 1.0v to + 4 . 5 v v in voltage on any signal pin with respect to v ss - 1.0v to + 4 . 5 v and v in < v dd +1v t stg storage temperature - 55 c to +125 c t lead lead temper ature (soldering, 10 seconds) 26 0 c v esd electrostatic discharge voltage - human body model (aec - q100 - 002 rev. e) - charged device model (aec - q100 - 011 rev. b) - machine model ( a ec - q100 - 003 rev. e ) tbd tbd tbd package moisture sensitivity level m sl - 3 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational sec tion of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliabil ity. dc operating conditions ( t a = - 40 c to + 85 c, v dd = 2.0 v to 3.6v unless otherwise specified) symbol parameter min typ max units notes v dd power supply 2.0 3.3 3.6 v i dd v dd supply current 7 12 ma 1 i sb standby current @ t a = 25 c @ t a = 85 c 12 0 - 150 25 0 a a 2 i zz sleep mode current @ t a = 25 c @ t a = 85 c 3 - 5 8 a a 3 i li input leakage curr ent 1 a 4 i lo output leakage current 1 a 4 v ih 1 input high voltage ( v dd =2.7v to 3.6v ) 2.2 v dd + 0.3 v v ih2 input high voltage ( v dd =2.0v to 2.7v ) 0.7 * v dd - v v il1 input low voltage ( v dd =2.7v to 3.6v ) - 0.3 0 .8 v v il2 input low voltage ( v dd =2 .0v to 2.7v ) - 0.3 0.3 * v dd v v oh1 output high voltage ( i oh = - 1 ma, v dd > 2.7v) 2.4 v v oh2 output high voltage ( i oh = - 100 a) v dd - 0.2 v v ol1 output low voltage ( i ol = 2 ma, v dd > 2.7v) 0.4 v v ol2 output low voltage ( i ol = 150 a) 0.2 v r in a ddress input resistance ( /zz) for v in = v ih (min) for v in = v il (max) 40 1 k m 5 notes 1. v dd = 3.6v, /ce cycling at min. cycle time. all inputs toggling at cmos levels (0.2v or v dd - 0.2v) , all dq pins unloaded. 2. v dd = 3.6v, /ce at v dd , all other pins are static and at cmos levels (0.2v or v dd - 0.2v), /zz is high. 3. v dd = 3.6v, /zz is low, all other inputs at cmos levels (0.2v or v dd - 0.2v). 4. v in , v out between v dd and v ss . 5. the input pull - up circuit is strong er (>4 0k ) when the inpu t voltage is above v i h and weak ( > 1 m ) when the input voltage is below v i l .
FM28V102 - 64kx16 f - ram document number: 001 - 86601 rev. ** page 9 of 1 6 read cycle ac parameters (t a = - 40 c to + 85 c, unless otherwise specified) v dd 2.0 to 2.7 v v dd 2.7 to 3.6 v symbol parameter min max min max units notes t rc read cycle time 105 - 90 - ns t ce chi p enable access time - 70 - 60 ns t aa address access time - 105 - 90 ns t oh output hold time 20 - 20 - ns t aap page mode address access time - 40 - 30 ns t ohp page mode output hold time 3 - 3 - ns t ca chip enable active time 70 - 60 - ns t pc pr echarge time 35 - 30 - ns t ba /ub, /lb access time - 25 - 15 ns t as address setup time (to / ce low ) 0 - 0 - ns t ah address hold time (/ce - controlled) 70 - 60 - ns t oe output enable access time - 25 - 15 ns t hz chip enable to output high - z - 15 - 10 ns 1 t ohz output enable high to output high - z - 15 - 10 ns 1 t bhz /ub, /lb high to output high - z - 15 - 10 ns 1 write cycle ac parameters (t a = - 40 c to + 85 c, unless otherwise specified) v dd 2.0 to 2.7 v v dd 2.7 to 3.6 v symbol parameter mi n max min max units notes t wc write cycle time 105 - 90 - ns t ca chip enable active time 70 - 60 - ns t cw chip enable to write enable high 70 - 60 - ns t pc precharge time 35 - 30 - ns t pwc page mode write enable cycle time 40 - 30 - ns t wp write enable pulse width 22 - 18 - ns t wp2 /ub, /lb pulse width 22 - 18 - ns t wp3 /we low to /ub, /lb high 22 - 18 - ns t as address setup time (to / ce low ) 0 - 0 - ns t ah address hold time (/ce - controlled) 70 - 60 - ns t asp page mode address setup tim e (to /we low) 8 - 5 - ns t ahp page mode address hold time (to /we low) 20 - 15 - ns t wlc write enable low to chip disabled 30 - 25 - ns t blc /ub, /lb low to chip disabled 30 - 25 ns t wla write enable low to a( 15: 2 ) change 30 - 25 - ns t awh a( 15 : 2 ) change to write enable high 105 - 90 - ns t ds data input setup time 20 - 15 - ns t dh data input hold time 0 - 0 - ns t wz write enable low to output high z - 10 - 10 ns 1 t wx write enable high to output driven 8 - 5 - ns 1 t bds byte disable setu p time (to /we low) 8 - 5 - ns t bdh byte disable hold time (to /we high ) 8 - 5 - ns notes 1. this parameter is characterized but not 100% tested. capacitance (t a = 25 c , f=1 mhz, v dd = 3.3v) symbol parameter min max units notes c i/o input/output ca pacitance (dq) - 8 pf c in input capacitance - 6 pf c zz input capacitance of /zz pin - 8 pf
FM28V102 - 64kx16 f - ram document number: 001 - 86601 rev. ** page 10 of 1 6 ac test condit ions input pulse levels 0 to 3v input and output timing levels 1.5v input r ise and f all t imes 3 ns output load capacitance 30pf read cycle ti ming 1 (/ ce low, /oe low) read cycle timing 2 (/ce - controlled) page mode read cycle timing although sequential column addressing is shown, it is not required. a ( 1 5 : 0 ) t r c t a a p r e v i o u s d a t a v a l i d d a t a t o h v a l i d d a t a t r c t a a t o h d q ( 1 5 : 0 ) a ( 1 5 : 0 ) d q ( 1 5 : 0 ) t a s t c e t h z t o e t o h t o h z u b / l b o e c e t b a t b h z t c a t p c t a h c e a ( 1 5 : 2 ) o e d q ( 1 5 : 0 ) t a s t c a a ( 1 : 0 ) t o e t c e t o h z t a a p t o h p t h z t p c d a t a 0 d a t a 1 d a t a 2 c o l 0 c o l 1 c o l 2
FM28V102 - 64kx16 f - ram document number: 001 - 86601 rev. ** page 11 of 1 6 wri te cycle timing 1 (/we - controlled ) note: /oe (not shown) is low only to show effect of /we on dq pins write cycle timing 2 (/ce - controlled) write cycle timing 3 (/ce low ) note: /oe (not sho wn) is low only to show effect of /we on dq pins d i n c e a ( 1 5 : 0 ) w e t c a t p c d q ( 1 5 : 0 ) t w p t c w t a s d o u t d o u t t d s t d h t w x t w z t h z t w l c c e a ( 1 5 : 0 ) w e d q ( 1 5 : 0 ) t a s t d h t d s d i n t c a t p c u b / l b t b l c d i n a ( 1 5 : 0 ) w e d q ( 1 5 : 0 ) t w c t d h t w l a t d s t a w h d o u t d o u t t w z t w x d i n
FM28V102 - 64kx16 f - ram document number: 001 - 86601 rev. ** page 12 of 1 6 write cycle timing 4 (/ce low ) note: / ub and /lb to show byte enable and byte masking cases. page mode write cycle timing although sequential column addressing is shown, it is not required. d i n a ( 1 5 : 0 ) w e d q ( 1 5 : 0 ) t d h t w p 3 d i n u b / l b t w p 2 t d s t d h t d s t b d h t b d s c e a ( 1 5 : 2 ) w e t c a t p c d q ( 1 5 : 0 ) t c w a ( 1 : 0 ) c o l 0 c o l 1 d a t a 0 c o l 2 t a s t d s d a t a 1 t w p t d h d a t a 2 o e t a h p t p w c t w l c t a s p
FM28V102 - 64kx16 f - ram document number: 001 - 86601 rev. ** page 13 of 1 6 power cycle and sleep mode enter/exit timing power cycle and sleep mode timing (t a = - 40 c to + 85 c, v dd = 2.0 v to 3.6v unless otherwise speci fied) symbol parameter min max units notes t pu power up (after v dd min. is reached) to first access time 1 - ms t pd last write (/we high) to power down time 0 - s t v r v dd rise time 5 0 - s/v 1,2 t v f v dd fall time 100 - s/v 1,2 t zzh /zz active to d q hi - z time - 20 ns t wezz last write to sleep mode entry time 0 - s t zzl /zz active low time 1 - s t zzen sleep mode entry time (/zz low to /ce dont care) - 0 s t zzex sleep mode exit time (/zz high to 1 st access after wakeup) - 450 s notes 1. s l ope measured at any point on v dd waveform . data retention ( t a = - 40 c to + 85 c) parameter min units notes data retention 10 years z z v d d m i n . v d d w e t p d c e d q r / w a l l o w e d t w e z z t z z l t p u d o u t t z z h d i n t z z e x r / w a l l o w e d t z z e n r / w a l l o w e d t z z e x v d d m i n .
FM28V102 - 64kx16 f - ram document number: 001 - 86601 rev. ** page 14 of 1 6 mechanical drawing 44 - pin tsop - ii (complies with jedec standard ms - 024 g var. ac) note: all dimensions in millimeters . tsop - ii package marking scheme legend: xxxxxx= part number, p=package , t=temperature (blank=ind., c=comm.) r=rev code, llllll= lot code, yy=year, ww=work week examples: fm 28v 102 , green/rohs tsop - ii pa ckage, rev a, lot 6340282, year 2 012, work week 25 ramtron fm 28v 102 - tg a 6340282 tg 1225 ramtron xxxxxxx - p t lllllll yyww p i n 1 1 0 . 1 6 b s c 1 . 2 0 m a x 0 . 1 0 m m 0 . 6 0 . 4 0 . 2 0 0 . 1 2 1 . 5 0 r e c o m m e n d e d p c b f o o t p r i n t 1 8 . 4 1 b a s i c 0 . 8 0 . 1 5 0 . 0 5 0 - 8 0 . 4 5 0 . 3 0 0 . 8 0 b s c 1 1 . 9 6 1 1 . 5 6 0 . 5 1 2 . 6
FM28V102 - 64kx16 f - ram document number: 001 - 86601 rev. ** page 15 of 1 6 revision history revision date summary 1.0 6/12/2012 initial release. ordering information part number features operating voltage operating temp. pack age fm28v 102 - tg 60 ns access, sleep mode 2.0 - 3.6v - 4 0c to + 85 c 44 - pin green/rohs tsop - ii document history document title: FM28V102 1 mbit (64k 16) f - ram memory document number: 001 - 86601 revision ecn orig. of change submissio n date description of chan ge ** 3930342 gvch 03/12/2013 new spec
FM28V102 - 64kx16 f - ram document number: 001 - 86601 rev. ** page 16 of 1 6 sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distribut ors. to find the office closest to you, visit us at cypress locations . products automotive cypress.com /go /a utomotive clocks & buffers cypress.com/go/clocks interface cypress.com/go /i nterface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.co m/go/memory psoc cypress.com/go/psoc touch sensing cypress.com/go/touch usb controllers cypress.com/go/usb p soc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 cypress developer community community | forums | blogs | video | training technical support cypress.com/go/ support ramtron is a registered trademark and nodelay? is a trademark of cypress semiconductor corp. all other trademarks or registered trademarks referenced herein are the property of their respective owners. ? cypress semi conductor co rporation, 2011 - 2013 . the information contained herein is subject to change without notice. cypress semiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress p roduct. nor does it convey or i mply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypr ess. further more, cypress does not authorize its products for use as critical components in life - support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life - support sy stems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. this source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by an d subject to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cy press hereby grants to licensee a personal, non - exclusive, non - transferable license to copy, use, modify, create deriv ative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in support of licen see product to be used only in conjunction with a cypress integrated circuit as specified in the ap plicable agreement. any reproduction, modification, translation, compilation, or representation of this source code except as specified above is prohibited without the express w ritten permission of cypress. disclaimer: cypress makes no warranty of any kind , express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to the materials described herein. cypress does no t assume any liability arisin g out of the application or use of any product or circuit described herein. cypress does not authorize its products for use as critical components in life - support systems where a malfunction or failure may reasonably be expected to result in significant in jury to the user. the inclusion of cypress product in a life - support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicab le cypress software license agreement.

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